An MOS transistor which combines selected features of prior art MOS devices made on bulk silicon is illustrated in the prior art drawings of FIGS. 1-6. It should be noted that no such device probably exists in all the details shown in these drawings. Instead, the surface geometry has been made as close as possible to the preferred embodiments of the present invention, in order to emphasize the similarities and dissimilarities between the "prior art" structure and the present invention.
The transistor is an NMOS type transistor and consists of an N-doped or P-doped silicon single crystal bulk substrate 12, which is part of a wafer 15 (only a portion of which is shown) and upon which a thin P-doped epitaxial film 9 is deposited by well-known techniques such as chemical vapor deposition (CVD).
Islands of device regions are formed in the film 9 by converting the volume around the device regions into thick regions of what is called field oxide 4.
The epitaxial film 9 is commonly grown to be the same type as is the choice for the base wafer 12 and then is converted to P-type (if necessary) for the P-well (or body) as required to operate the NMOS transistor. The transistor is formed by a source region 2 a drain region 1 a polysilicon gate 3, polysilicon oxide spacers 5a thin gate oxide 5, a polysilicon interconnect to the drain 6 a silicide strap 7 for contacting the drain to its polysilicon interconnect 6 and body contact opening 8 to body 9. Thick field oxide regions 4 are shown as the result of a trench and refill process in FIGS. 1-5, while FIG. 6 shows the corresponding cross-section of the conventional NMOS drain (taken along V--V of FIG. 2) if made with a conventional LOCOS process Note that in FIG. 6, the interface wall 100 of the field oxide 40 is tapered. FIG. 3 is cross section III--III illustrating the inclusion of lightly doped region 13 around each of the source and drain regions as this is a common practice with contemporary manufacturing techniques for NMOS transistors.
The thick field oxides 4 enable conductive interconnect pathways (not shown) on the surface of the wafer to pass from one MOS transistor to another on the wafer without causing surface inversion in the wafer's silicon-to-oxide interface. Should this field oxide not be amply thick charge inversion in the silicon surface directly below these interconnect pathways will occur which result in the creation of undesired MOS transistor conducting channels which pass electrical currents between pairs of MOS transistors as a function of the voltage difference applied between the interconnect pathways and the silicon surface regions.
Present-day fabrication methods commonly use a field oxide for separating transistors. The field oxide has a thickness greater than the minimum thickness at which the maximum applied integrated circuit operating voltage difference will not cause charge inversion in the silicon surface below any pathway interconnecting transistors. The basis for this determination are well understood by those skilled in the art, and are dependent on silicon surface doping concentrations and of course, electric field strengths in the surface oxides which are directly proportional to applied voltage and inversely proportional to field oxide thickness.
In addition to field oxides conventional MOS transistors also require a thin oxide gate layer 5 to separate the polysilicon gate electrode 3 from the source region 2 and drain region 1 on either side of the gate 3.
In all cases of known process implementations the field oxides are thicker than the oxides 5 used to form the gates of the MOS transistors themselves Of course it is in these gate oxide regions where a conducting "channel" in the silicon surface is desired This difference in oxide thicknesses thereby enables the circuit designer to precisely determine the physical location of each MOS transistor's conducting channel while permitting the interconnection of a plurality of transistors together over field oxides without creating a network of undesired conducting channels which are function of the final transistor-to-transistor layout. As a result designers are able to utilize design automation systems to fully predict the performance of a proposed design before the chip layout is done which greatly simplifies the design process for circuits requiring more than 100 transistors.
Two advanced methods for forming thick field oxides are employed: local oxidation of silicon or LOCOS or the formation of oxide-filled trench regions between transistors. LOCOS is more commonly employed. Both methods customarily use a heavy concentration of P type dopant (such as boron) to (a) assist in the rapid formation of thick field oxides, and (b) to electrically stabilize the silicon-to-oxide interface for the purpose of reducing leakage currents of any P-N junctions which meet these interfaces. The use of boron in this manner enables the reduction of separation distances between devices, as well as minimizing leakage currents in P-N junctions. These leakage currents become primary considerations for power dissipation minimization for integrated MOS circuits requiring greater than 100,000 transistors.
It is with these very-large-scale-integrated (VLSI) circuits that either LOCOS or trench-type oxidations are employed to prevent undesired conduction between pairs of transistors. Either of these oxidations use a P type dopant in the process which results in the formation of a heavily-doped P type or P+ layer 10 between the thick field oxide and the epitaxial film 9.
In the case of NMOS transistors, this P type layer 10 creates a P-N junction to the heavily-doped N type regions or N+ commonly used for the NMOS source 2 and drain 1 regions. This N to P junction is required to stabilize a VLSI circuit for low leakage currents and is commonly formed in the prior art methods and defines the dominant coupling capacitance of each N+ source and drain region to the NMOS transistor's P type body region.